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The N32G003 series features a 32-bit Arm® Cortex®-M0 core, with a maximum operating frequency of 48MHz. It integrates up to 29.5KB Flash, 3KB SRAM, 1 12-bit 1Msps ADC, 1 comparator (COMP), 2 UARTs, 1 I2C, and 1 SPI interface.
• Arm® Cortex®-M0 @48MHz
• Storage:
- Up to 29.5KBytes on-chip Flash, 100,000 erase/write cycles, 10-year data retention.
- 3KBytes on-chip SRAM.
• Power Management:
- Run Mode: All peripherals configurable.
- Stop Mode: TIM6, IWDG configurable operation, SRAM data retention, all IO state retention.
- Power Down Mode: All power off, supports wake-up via NRST, PA1_WKUP0, PA2_WKUP1.
• Clock: Supports internal RC crystal clock.
• Reset:
- Supports power-on/power-off/external pin reset.
- Supports programmable low-voltage detection reset.
- Supports watchdog reset, software reset.
• Communication Interfaces:
- 2 UART interfaces, supports asynchronous mode, multiprocessor communication mode, single-wire half-duplex mode.
- 1 SPI interface, up to 12MHz.
- 1 I2C interface, up to 1MHz, configurable as master or slave.
• Analog Interfaces:
- 1 12-bit 1Msps high-speed ADC, supports up to 9 external single-ended input channels, 1 internal channel connected to 1.2V reference.
- 1 high-speed analog comparator, positive input supports four adjustable voltage differences: 0mV/100mV/200mV/300mV.
• GPIO: Supports up to 18 multiplexed GPIOs.
• Buzzer: Supports complementary output.
• Timers and Counters:
- 1 16-bit advanced timer supports 6 complementary PWM outputs.
- 1 16-bit general-purpose timer supports input capture/output compare/PWM output.
- 1 16-bit basic timer supports wake-up from STOP low-power mode.
- 1 24-bit SysTick.
- 1 12-bit independent watchdog (IWDG).
• Security Features:
- Supports CRC16 calculation.
- Supports multiple read protection (RDP) levels (L0/L1/L2).
• Identification:
- 96-bit UID and 128-bit UCID.
• High-Reliability Operating Environment:
- 2V to 5.5V / -40℃ to 105℃.
- ESD: ±4kV (HBM model).
N32G003 Product Brief
N32G003 Datasheet
N32G003 Series User Manual
N32G003 Errata Sheet
N32G003 Safety Startup
Setting up the GCC development environment for the N32G003 series
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