• Core

―  A 32-bit general-purpose microcontroller based on the Arm® Cortex®-M0 core, Single-cycle hardware multiply instruction

― Run up to 64MHz

• Encrypted memory

―  Up to 128KByte embedded Flash memory, 8KByte embedded Data Flash memory, supports encrypted storage, supports hardware ECC verification, data 100,000 cycling and 10 years of data retention

―  SRAM of 16KB, STOP modes can be configured as retention, supporting hardware parity

• Low-power management

―  Run mode: all peripherals configurable

―  SLEEP mode: all peripherals configurable

―  STOP mode: TIM6, IWDG, RTC configurable operation, 16KByte SRAM retention, CPU register retention, all IO retention

―  Power Down mode: support NRST, PA0_WKUP0, PA2_WKUP1 wakeup

• Clock

―  HSE: 8MHz~16MHz external high-speed crystal

―  HSI: Internal high-speed RC OSC 8MHz

―  HSI_24MHz: Internal high-speed RC OSC 24MHz, available only as an ADC sample clock source option

―  LSI: Internal low-speed RC OSC 32KHz

―  Built-in high-speed PLL

―  MCO: Support 1-way clock output, configurable SYSCLK, HSI, HSE, LSI, and PLL clock output that can be divided.

• Reset

―  Support power-on/power-off/external pin reset

―  Supports programmable low voltage detection reset(LVR)

―  Support watchdog reset, Support software reset

• Communication interface

―  5xUART, Supports asynchronous mode, multiprocessor communication mode, single-wire half-duplex mode

―  3xSPI, up to 16 MHz

―  2xI2C, up to 1 MHz, configurable master/slave mode

―  1xCAN 2.0A/B bus interface, up to 1Mbps

• 1xDMA, 5-channel, channel source address and destination address can be arbitrarily configurable 

• 1x RTC real-time clock, support leap year perpetual calendar, alarm event, periodic wake up, support internal and external clock calibration

• Segment LCD display driver, support up to 44 segments (4x11) or 26 segments (2x13)