/**
*     Copyright (c) 2025, Nsing Technologies Inc.
* 
*     All rights reserved.
*
*     This software is the exclusive property of Nsing Technologies Inc. (Hereinafter 
* referred to as Nsing). This software, and the product of Nsing described herein 
* (Hereinafter referred to as the Product) are owned by Nsing under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
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* intellectual property rights. Names and brands of third party may be mentioned or referred 
* thereto (if any) for identification purposes only.
*
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* improvements to this software at any time without notice. Please contact Nsing and obtain 
* the latest version of this software before placing orders.

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* no responsibility for the accuracy and reliability of this software.
* 
*     It is the responsibility of the user of this software to properly design, program, and test 
* the functionality and safety of any application made of this information and any resulting product. 
* In no event shall Nsing be liable for any direct, indirect, incidental, special,exemplary, or 
* consequential damages arising in any way out of the use of this software or the Product.
*
*     Nsing Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property 
* damage. Such applications are deemed, "Insecure Usage".
*
*     All Insecure Usage shall be made at user's risk. User shall indemnify Nsing and hold Nsing 
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*
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**/

/**
*\*\file n32g033_it.c
*\*\author Nsing
*\*\version v1.0.0
*\*\copyright Copyright (c) 2025, Nsing Technologies Inc. All rights reserved.
**/


#include "n32g033_it.h"
#include "main.h"


/** Cortex-M0 Processor Exceptions Handlers **/

/**
*\*\name    NMI_Handler.
*\*\fun     This function handles NMI exception.
*\*\param   none
*\*\return  none 
**/
void NMI_Handler(void)
{
}

/**
*\*\name    HardFault_Handler.
*\*\fun     This function handles Hard Fault exception.
*\*\param   none
*\*\return  none 
**/
void HardFault_Handler(void)
{
    /* Go to infinite loop when Hard Fault exception occurs */
    while (1)
    {
    }
}


/**
*\*\name    SVC_Handler.
*\*\fun     This function handles SVCall exception.
*\*\param   none
*\*\return  none 
**/
void SVC_Handler(void)
{
}

/**
*\*\name    PendSV_Handler.
*\*\fun     This function handles PendSV_Handler exception.
*\*\param   none
*\*\return  none 
**/
void PendSV_Handler(void)
{
}

/**
*\*\name    SysTick_Handler.
*\*\fun     This function handles SysTick Handler.
*\*\param   none
*\*\return  none 
**/
void SysTick_Handler(void)
{
}


/* n32g033 Peripherals Interrupt Handlers, interrupt handler's name please refer to the startup file (startup_n32g033.s). */

#define BufferSize 32
extern __IO uint8_t TxIdx, RxIdx;
extern uint8_t MASTER_Buffer_Tx[BufferSize], SLAVE_Buffer_Rx[BufferSize];


/**
*\*\name    SPI1_IRQHandler.
*\*\fun     This function handles SPI1 global interrupt request.
*\*\param   none
*\*\return  none 
**/
void SPI1_IRQHandler(void)
{
    if (SPI_GetIntStatus(SPI_MASTER, SPI_INT_FLAG_TE) != RESET)
    {
        /* Send SPI_MASTER data */
        SPI_TransmitData(SPI_MASTER, MASTER_Buffer_Tx[TxIdx++]);

        /* Disable SPI_MASTER TE interrupt */
        if (TxIdx == BufferSize)
        {
            SPI_EnableInt(SPI_MASTER, SPI_INT_TE, DISABLE);
        }
    }
}

/**
*\*\name    SPI2_IRQHandler.
*\*\fun     This function handles SPI2 global interrupt request.
*\*\param   none
*\*\return  none 
**/
void SPI2_IRQHandler(void)
{
    if(SPI_GetIntStatus(SPI_SLAVE, SPI_INT_FLAG_RNE) != RESET)
    {
        /* Store SPI_SLAVE received data */
        SLAVE_Buffer_Rx[RxIdx++] = SPI_ReceiveData(SPI_SLAVE);
    }
}

