1˵
    1TIM2 ſTIM3 TIM4
2ʹû
    KEIL MDK-ARM V5.34.0.0
    Ӳ 
        N32G05xϵУ
            N32G05xRBQ7_STB V1.0
        N32G05xϵУ
            N32G05xRBL7_STB V1.0
3ʹ˵
    ϵͳ:
        1ʱԴ
                    HSI=8M,SYS CLK=64M,TIM2 CLK=64M
        2˿ã
                    PA10ѡΪTIM2CH1
                    PA8ѡΪTIM3CH1
                    PB6ѡΪTIM4CH1
        3TIM
                    TIM2 ڴſTIM3 TIM4CH1,TIM3Ϊ10TIM2TIM4Ϊ5TIM2
    ʹ÷
        1򿪵ģʽʾ߼ǹ۲TIM2 CH1TIM3 CH1TIM4 CH1Ĳ
        2TIM45TIM2TIM310TIM2
4ע
       ĬPA9,PA10ñӵNSLINK⴮ڣPA9PA10ڣ;εñ
	
	
	
1. Function description
     1. TIM2 cycle gated TIM3 TIM4
2. Use environment
	Software development environment: KEIL MDK-ARM V5.34.0.0
    Hardware development environment:
         N32G05x series:
            Developed based on the evaluation board N32G05xRBQ7_STB V1.0
         N32G05x series:
            Developed based on the evaluation board N32G05xRBL7_STB V1.0
3. Instructions for use
    System Configuration;
        1. Clock source:
                    HSI=8M,SYS CLK=64M,TIM2 CLK=64M
         2. Port configuration:
                     PA10 is selected as CH1 output of TIM2
                     PA8 is selected as the CH1 output of TIM3
                     PB6 is selected as the CH1 output of TIM4
         3. TIM:
                     TIM2 cycle triggers CH1 of gating TIM3 TIM4, that is, TIM3 is 10 times period TIM2, that is, TIM4 is 5 times period TIM2
     Instructions:
         1. After compiling, turn on the debug mode and use an oscilloscope or logic analyzer to observe the waveforms of TIM2 CH1, TIM3 CH1, and TIM4 CH1
         2. The cycle of TIM4 is 5 times that of TIM2, and the cycle of TIM3 is 10 times that of TIM2.
4. Matters needing attention
        By default, the PA9 and PA10 jumper caps of the development board are connected to the virtual serial port of NSLINK. If PA9 and PA10 are not used as serial ports in the project, and are used for other purposes, the serial port jumper caps must be unplugged.
	