1˵
    1TIM1 һںͬʱıںռձ
2ʹû
    KEIL MDK-ARM V5.34.0.0
    Ӳ 
        N32G05xϵУ
            N32G05xRBQ7_STB V1.0
        N32G05xϵУ
            N32G05xRBL7_STB V1.0
3ʹ˵
    ϵͳ:
        1ʱԴ
                    HSI=8M,SYS CLK=64M,TIM1 CLK=64M
        2˿ã
                    PA4ѡΪTIM1 CH1
        3TIM
                    TIM1 CH1 ڴDMA burst䣬CCDAT1CCDAT2CCDAT3CCDAT4CCDAT5CCDAT6PSC, ARĴıռձȺںظ
        4DMA
                    DMA1_CH5ͨѭģʽ8SRC_Buffer[8]TIM1 DMAĴ
    ʹ÷
        1򿪵ģʽʾ߼ǹ۲TIM1 CH1Ĳ
        2TIM1ĵһڽ󣬺ĲΪDMA˵ĸıںռձȵĲ
        3״̬޸DmaAgain=1ٴΰ8SRC_Buffer[8]TIM1 DMAĴ
4ע
    
	
	
	
1. Function description
     1. TIM1 changes the period and duty cycle at the same time after one cycle
2. Use environment
	Software development environment: KEIL MDK-ARM V5.34.0.0
    Hardware development environment:
         N32G05x series:
            Developed based on the evaluation board N32G05xRBQ7_STB V1.0
         N32G05x series:
            Developed based on the evaluation board N32G05xRBL7_STB V1.0	
3. Instructions for use
    System Configuration;
        1. Clock source:
                    HSI=8M,SYS CLK=64M,TIM1 CLK=64M
        2. Port configuration:
            PA4 selected as TIM1 CH1 Output
        3. TIM:
            TIM1 CH1 output, periodically triggered DMA burst transmission, loading CCDAT1CCDAT2CCDAT3CCDAT4CCDAT5CCDAT6PSC, AR registers, changing duty cycle, period and repeat counter
        4. DMA:
            DMA1_ CH5 Channel circular mode handling 8 word SRC_ Buffer[8] variable to TIM1 DMA register
     Instructions:
         1. After compiling, turn on the debug mode, and use an oscilloscope or logic analyzer to observe the waveform of TIM1 CH1
         2. After the first cycle of TIM1 is over, the following waveforms are the waveforms of changing cycle and duty cycle of DMA transport
         3. Modifying DmaAgain=1 in the debug state will again carry the 8 word SRC_Buffer[8] variable to the TIM1 DMA register
4. Matters needing attention
    None