1˵
    1TIM2ſTIM3TIM3ſTIM4    
2ʹû
    KEIL MDK-ARM V5.34.0.0
    Ӳ 
        N32G05xϵУ
            N32G05xRBQ7_STB V1.0
        N32G05xϵУ
            N32G05xRBL7_STB V1.0

3ʹ˵
    ϵͳ:
        1ʱԴ
                    HSI=8M,SYS CLK=64M,TIM2 CLK=64M,TIM3 CLK=64M,TIM4 CLK=64M
        2˿ã
                    PA10ѡΪTIM2 CH1
                    PA8ѡΪTIM3 CH1
                    PB6ѡΪTIM4 CH1
        3TIM
                    TIM2 ſTIM3TIM3ſTIM4
    ʹ÷
        1򿪵ģʽʾ߼ǹ۲TIM2 CH1TIM3 CH1TIM4 CH1
        2TIM3 4TIM2TIM4 4TIM3
4ע
       ĬPA9,PA10ñӵNSLINK⴮ڣPA9PA10ڣ;εñ
	
	
	
1. Function description
     1. TIM2 cycle gate TIM3, TIM3 cycle gate TIM4
2. Use environment
	Software development environment: KEIL MDK-ARM V5.34.0.0
    Hardware development environment:
         N32G05x series:
            Developed based on the evaluation board N32G05xRBQ7_STB V1.0
         N32G05x series:
            Developed based on the evaluation board N32G05xRBL7_STB V1.0
3. Instructions for use
    System Configuration;
        1. Clock source:
                    HSI=8M,SYS CLK=64M,TIM2 CLK=64M,TIM3 CLK=64M,TIM4 CLK=64M
         2. Port configuration:
                     PA10 is selected as TIM2 CH1 output
                     PA8 is selected as TIM3 CH1 output
                     PB6 is selected as TIM4 CH1 output
         3. TIM:
                     TIM2 cycle gating TIM3, TIM3 cycle gating TIM4
     Instructions:
         1. After compiling, turn on the debug mode, and use an oscilloscope or logic analyzer to observe the waveforms of TIM2 CH1, TIM3 CH1, and TIM4 CH1
         2. TIM3 4 times cycle TIM2, TIM4 4 times cycle TIM3
4. Matters needing attention
        By default, the PA9 and PA10 jumper caps of the development board are connected to the virtual serial port of NSLINK. If PA9 and PA10 are not used as serial ports in the project, and are used for other purposes, the serial port jumper caps must be unplugged.