1˵
    1ADCתPA2ŵģѹģ⿴ŹֵΧжϳ
2ʹû
      KEIL MDK-ARM V5.30.0.0
    Ӳ      N32G003F5S7-STB V1.0
3ʹ˵
    ϵͳã
        1ʱԴ
                    HSI=48M,AHB=48M,APB1=48M,ADC CLK=48M/12,ADC 1M CLK=HSI/48
        2ADC
                    ADCת12λҶ룬ADCͨ1
		3˿ã
                    PA2ѡΪģ⹦ADCתͨ0
		4жϣ
                    ADCģ⿴Źжϴ򿪣ȼ0
    ʹ÷
        1򿪵ģʽgCntAwdgӵwatchڹ۲
        2ıPA2ŵѹֵѹֵģ⿴Ź0x3000.6V0xB002.26VΧ⣬һжϣۼӲ
4ע
    1.ϵͳʱHSIΪ48MʱRCC_ADC_1M_Clock_Config(RCC_ADC1MCLK_DIV48)ƵҪóRCC_ADC1MCLK_DIV48
    2.ϵͳʱHSIΪ40MʱRCC_ADC_1M_Clock_Config(RCC_ADC1MCLK_DIV40)ƵҪóRCC_ADC1MCLK_DIV40



1. Function description
    1. ADC samples and converts the analog voltage of the PA2 pin. If it exceeds the threshold range defined by the analog watchdog, then jump into the interrupt program

2. Use environment
    Software development environment: KEIL MDK-ARM V5.30.0.0
    Hardware environment: Developed based on the evaluation board N32G003F5S7-STB V1.0

3. Instructions for use
    System Configuration;
        1. Clock source:
                    HSI=48M,AHB=48M,APB1=48M,ADC CLK=48M/12,ADC 1M CLK=HSI/48
        2. ADC:
                    ADC configuration: continuous conversion, software trigger, 12-bit data right-aligned, ADC channel 1.
        3. Port configuration:
                    PA2 is selected as analog function, ADC conversion channel 0
        4. Interrupt:
                    ADC analog watchdog interrupt is turned on, priority 0
    Instructions:
        1. Open the debug mode after compiling and add the variable gCntAwdg to the watch window for observation
        2. Change the voltage value of the PA2 pin. When the voltage value exceeds the range defined by the analog watchdog from 0x300 (ie 0.6V) to 0xB00 (ie 2.26V), an interrupt is entered, and the variable is accumulated

4. Matters needing attention
    1.When the system sampling clock HSI is 48M, RCC_ADC_1M_Clock_Config(RCC_ADC1MCLK_DIV48), frequency division needs to be configured as RCC_ ADC1MCLK_ DIV48
    2.When the system sampling clock HSI is 40M, RCC_ADC_1M_Clock_Config(RCC_ADC1MCLK_DIV40), frequency division needs to be configured as RCC_ ADC1MCLK_ DIV40