1˵
    1TIM1 ſTIM3
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      KEIL MDK-ARM V5.34.0.0
    Ӳ      N32G031C8L7-STB V1.0
3ʹ˵
    ϵͳ:
        1ʱԴ
                    HSE=8M,PLL=48M,AHB=48M,APB1=48M,APB2=48M,TIM1 CLK=48M,TIM3 CLK=48M
        2˿ã
                    PA8ѡΪTIM1CH1
                    PA4ѡΪTIM3CH1
        3TIM
                    TIM1 ڴſTIM3 CH1,TIM3Ϊ10TIM1
    ʹ÷
        1򿪵ģʽʾ߼ǹ۲TIM1 CH1TIM3 CH1Ĳ
        2TIM310TIM1
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/*** For English users   ***/
1. Function description
    1. TIM1 cycle gated TIM3
2. Use environment
    Software development environment: KEIL MDK-ARM V5.34.0.0
    Hardware environment: Developed based on the evaluation board N32G031C8L7-STB V1.0
3. Instructions for use
    System configuration:
        1. Clock source:
            HSE=8M, PLL=48M, AHB=48M, APB1=48M, APB2=48M, TIM1 CLK=48M, TIM3 CLK=48M
        2. Port configuration:
            PA8 is selected as CH1 output of TIM1
            PA4 is selected as CH1 output of TIM3
        3. TIM:
            TIM1 cycle triggers CH1 of gated TIM3, i.e. TIM3 is 10 times cycle in TIM1
Usage method:
    1. Open debugging mode after compilation and observe TIM1 CH1, TIM3 CH1 waveforms with oscilloscope or logic analyzer
         2. The cycle of TIM3 is 10 times that of TIM1
4. Matters needing attention
    None