1˵
    1TIM1 CH3 CH3Nźÿ6ڸıһռձ
2ʹû
      KEIL MDK-ARM V5.34.0.0
    Ӳ      N32G031C8L7-STB V1.0
3ʹ˵
    ϵͳ:
        1ʱԴ
                HSE=8M,PLL=48M,AHB=48M,APB1=48M,APB2=48M,TIM1 CLK=48M,DMA CLK=48M
        2˿ã
                PA10ѡΪTIM1 CH3
                PB15ѡΪTIM1 CH3N
        3TIM
                TIM1 CH3 CH3Nÿ6ڴһDMA
        4DMA
                DMA1_CH5ͨػģʽ3SRC_Buffer[3]TIM1 CCDAT3Ĵ
    ʹ÷
        1򿪵ģʽʾ߼ǹ۲TIM1 CH3 CH3NĲ
        2TIM16ڸıһCH3 CH3Nռձȣѭı
4ע
    

1. Functional description
    1. TIM1 CH3 CH3N complementary signal changes duty cycle every 6 cycles
2. Use environment
    Software development environment: KEIL MDK-ARM V5.34.0.0
    Hardware environment: Developed based on the evaluation board N32G031C8L7-STB V1.0
3. Instructions for Use
    System configuration:
        1. Clock source:
            HSE=8M, PLL=48M, AHB=48M, APB1=48M, APB2=48M, TIM1 CLK=48M, DMA CLK=48M
        2. Port configuration:
            PA10 selected as TIM1 CH3 Output
            PB15 selected as TIM1 CH3N Output
        3. TIM:
            TIM1 CH3 CH3N complementary output triggers DMA transmission every 6 cycles
        4. DMA:
            DMA1_ CH5 Channel circular mode handling 3 half-Word SRC_ Buffer[3] variable to TIM1 CCDAT3 register
     Instructions:
         1. After compiling, turn on the debug mode, use an oscilloscope or logic analyzer to observe the waveform of TIM1 CH3 CH3N
         2. Change the duty cycle of CH3 and CH3N once in 6 cycles of TIM1, and change cyclically
4. Matters needing attention
    None